{"id":101090,"date":"2018-03-11T10:22:47","date_gmt":"2018-03-11T10:22:47","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/a-multi-tier-cached-i-o-architecture-for-massively-parallel-supercomputers\/"},"modified":"2018-03-11T10:22:47","modified_gmt":"2018-03-11T10:22:47","slug":"a-multi-tier-cached-i-o-architecture-for-massively-parallel-supercomputers","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/arquitectura-de-ordenadores\/a-multi-tier-cached-i-o-architecture-for-massively-parallel-supercomputers\/","title":{"rendered":"A multi-tier cached i\/o architecture for massively parallel supercomputers"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Francisco Javier Garc\u00eda Blas <\/strong><\/h2>\n<p>Recent advances in storage technologies and high performance interconnects have  made possible in the last years to build, more and more potent storage systems that serve  thousands of nodes. The majority of storage systems of clusters and supercomputers from top  500 list are managed by one of three scalable parallel file systems: gpfs, pvfs and lustre.   most large scale scientific parallel applications are written in message  passing interface (mpi), which has become the de-facto standard for scalable distributed  memory machines. One part of the mpi standard is related to i\/o and has among its main  goals the portability and efficiency of file system accesses. All of the above mentioned  parallel file systems may be accessed also through the mpi-io interface.   the i\/o access patterns of scientific parallel applications often consist of accesses to a large  number of small, non-contiguous pieces of data.  For small file accesses the performance is  dominated by the latency of network transfers and disks. Parallel scientific applications  lead to interleaved file access patterns with high interprocess spatial locality at the i\/o nodes.    additionally, scientific applications exhibit repetitive behaviour when a loop or a function with loops  issues i\/o requests. When i\/o access patterns are repetitive, caching and prefetching can effectively  mask their access latency. These characteristics of the access patterns motivated several  researchers to propose parallel i\/o optimizations both at library and file system levels.  However, these  optimizations are not always integrated across different layers in the systems.  in this dissertation we propose a novel generic parallel i\/o architecture for clusters and  supercomputers.  Our design is aimed at large-scale parallel architectures with thousands  of compute nodes. Besides acting as middleware for existing parallel file systems, our architecture  provides on-line virtualization of storage resources. Another objective of this thesis is to factor out  the common parallel i\/o functionality from clusters and supercomputers in generic modules in order  to facilitate porting of scientific applications across these platforms.   our solution is based on a multi-tier cache architecture, collective i\/o,  and asynchronous data staging strategies hiding the latency of data transfer between cache tiers.  the thesis targets to reduce the file access latency perceived by the data-intensive parallel scientific  applications by multi-layer asynchronous data transfers.  In order to accomplish this objective, our  techniques leverage the multi-core architectures by overlapping computation with communication  and i\/o in parallel threads.   prototypes of our solutions have been deployed on both clusters and blue gene supercomputers.  Performance  evaluation shows that the combination of collective strategies with overlapping of computation, communication,  and i\/o may bring a substantial performance benefit for access patterns common for parallel scientific applications.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>A multi-tier cached i\/o architecture for massively parallel supercomputers<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 A multi-tier cached i\/o architecture for massively parallel supercomputers <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Francisco Javier Garc\u00eda Blas <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Carlos III de Madrid<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 25\/05\/2010<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Jes\u00fas Carretero P\u00e9rez<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: f\u00e9lix Garc\u00eda carballeira <\/li>\n<li>rosa Mar\u00eda Badia sala (vocal)<\/li>\n<li>raffaele Montella (vocal)<\/li>\n<li>enrique salvador Quintana orti (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Francisco Javier Garc\u00eda Blas Recent advances in storage technologies and high performance interconnects have made possible in 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