{"id":11073,"date":"2001-01-06T00:00:00","date_gmt":"2001-01-06T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/diseno-e-implementacion-de-arquitecturas-dinamicamente-reconfigurables-basadas-en-microprocesador\/"},"modified":"2001-01-06T00:00:00","modified_gmt":"2001-01-06T00:00:00","slug":"diseno-e-implementacion-de-arquitecturas-dinamicamente-reconfigurables-basadas-en-microprocesador","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/ciencias-tecnologicas\/diseno-e-implementacion-de-arquitecturas-dinamicamente-reconfigurables-basadas-en-microprocesador\/","title":{"rendered":"Dise\u00f1o e implementacion de arquitecturas dinamicamente reconfigurables basadas en microprocesador"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Julio Faura Enriquez <\/strong><\/h2>\n<p>Esta tesis estudia la metodolog\u00eda del dise\u00f1o, implementaci\u00f3n fisica y utilizaci\u00f3n de arquitecturas programables genericas que permitirian en la implementacion rapida y barata de aplicaciones de tipo industrial de se\u00f1al mixta basadas en microprocesador. Este tipo de arquitecturas, denominadas genericamente fipsocs (fled programmable system on a chip), contendrian un substrato programable (un fpga) para la parte digital del dise\u00f1o, un conjunto de celula analogicas programables para las tareas de interfaz con se\u00f1ales analogicas, y un microprocesador orientado a operaciones de control y computacion de proposito general, y dispondrian de una metodolog\u00eda integrada consistente de dise\u00f1o, programacion y verificacion.  en particular se estudian no s\u00f3lo los aspectos arquitecturales de cada uno de estos tres boques por separado sino los relativos a su integraaci\u00f3n con el objeto de maximizar la interacci\u00f3n entre ellos, adem\u00e1s de los aspectos metodologicos derivados de esta fuerte interaccion. De esta forma se explotan ideas tales como el acceso en tiempo real a las se\u00f1ales del circuito desde posiciones de memoria de datos del microprocesador, lo que permite una co-emulaci\u00f3n conjunta hardware-software en tiempo pseudo-real integrada lo cual supone una nueva metodolog\u00eda de dise\u00f1o y verificacion, se propone ademas un esquema de memoria de configuraci\u00f3n en el que cada bit de programacion estaria precedido de una o varias celulas de memoria buffer accesibles como memoria normal desde el mircroprocesador, lo cual posibilita la reconfiguracion dinamica multicontexto tanto parcial como total sin necesidad de detener el funcionamiento de la parte de circuito reconfigurada, y la reutilizacion de memoria para objetivos adicionales a la configuracion del chip. Este de substrato dinamicamente reconfigurable resulta ideal para explorar tecnicas de hardware virtual que permitirian maximizar la utilizacion del silicio activo en cada momento.  finalme<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Dise\u00f1o e implementacion de arquitecturas dinamicamente reconfigurables basadas en microprocesador<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Dise\u00f1o e implementacion de arquitecturas dinamicamente reconfigurables basadas en microprocesador <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Julio Faura Enriquez <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Aut\u00f3noma de Madrid<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 01\/06\/2001<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Eduardo Boemo Scalvinoni<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Antonio Garcia guerra <\/li>\n<li>Antonio  Jes\u00fas Torralba silgado (vocal)<\/li>\n<li>eduardo Sanchez mejia (vocal)<\/li>\n<li>Francisco Jos\u00e9 Pelayo valle (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Julio Faura Enriquez Esta tesis estudia la metodolog\u00eda del dise\u00f1o, implementaci\u00f3n fisica y utilizaci\u00f3n de arquitecturas programables [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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