{"id":110926,"date":"2018-03-11T10:37:15","date_gmt":"2018-03-11T10:37:15","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/castell-a-heterogeneous-cmp-architecture-scalable-to-hundreds-of-processors\/"},"modified":"2018-03-11T10:37:15","modified_gmt":"2018-03-11T10:37:15","slug":"castell-a-heterogeneous-cmp-architecture-scalable-to-hundreds-of-processors","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/arquitectura-de-ordenadores\/castell-a-heterogeneous-cmp-architecture-scalable-to-hundreds-of-processors\/","title":{"rendered":"Castell: a heterogeneous cmp architecture scalable to hundreds of processors"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Felipe Cabarcas Jaramillo <\/strong><\/h2>\n<p>Debido a las mejoras tecnol\u00f3gicas y limitaciones en consumo de potencia de los microprocesadores, las arquitecturas multi-n\u00facleo est\u00e1n dominando el mercado y desplazando a los procesadores de un solo n\u00facleo. Al mismo tiempo, las arquitecturas basadas en aceleradores han  mostrado que los procesadores multi-n\u00facleo heterog\u00e9neos son muy eficientes y pueden proporcionar alto rendimiento en aplicaciones paralelas, pero a costa de un incremento en el esfuerzo para ser programados. Nosotros proponemos castell, una arquitectura multi-n\u00facleo escalable que puede ser programada como si fuera un procesador con un solo n\u00facleo, pero con el rendimiento de una arquitectura basada en aceleradores. castell se apoya en los modelos de programaci\u00f3n basados en tareas, que simplifican el desarrollo de software para multiprocesadores. Estos modelos usan un sistema en tiempo de ejecuci\u00f3n que identifica y planifica las tareas, y las enriquece con caracter\u00edsticas particulares del hardware. Una de estas caracter\u00edsticas son las transferencias dma, que permiten solapar computaci\u00f3n y transferencia de datos mediante double-buffering. Esta caracter\u00edstica permite que las aplicaciones en castell toleren grandes latencias de memoria y nos permiten centrar el dise\u00f1o del sistema de memoria en el ancho de banda. adem\u00e1s de la programabilidad y el dise\u00f1o del sistema de memoria, se ha dise\u00f1ado una red de interconexi\u00f3n jer\u00e1rquica y se ha a\u00f1adido un modulo de sincronizaci\u00f3n. La red de interconexi\u00f3n distribuye eficientemente el tr\u00e1fico de memoria para permitir que la arquitectura escale. El m\u00f3dulo de sincronizaci\u00f3n es una consecuencia de la gran degradaci\u00f3n de desempe\u00f1o de las aplicaciones como consecuencia de las grandes latencias de la sincronizaci\u00f3n por software. Castell es, principalmente, una arquitectura marco que permite la definici\u00f3n de implementaciones espec\u00edficas para un dominio particular. Hasta el momento, castell ha sido usada para proponer arquitecturas heterog\u00e9neas para aplicaciones cient\u00edficas, decodificaci\u00f3n de v\u00eddeo (usando h.264), y alineaci\u00f3n de secuencias de prote\u00ednas (usando el algoritmo de smith-waterman y clustalw). Adem\u00e1s, ha sido usada para explorar optimizaciones para las arquitecturas: como un dma mejorado y soporte hardware para el manejo de tareas en modelos de programaci\u00f3n basado en \u00e9stas.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Castell: a heterogeneous cmp architecture scalable to hundreds of processors<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Castell: a heterogeneous cmp architecture scalable to hundreds of processors <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Felipe Cabarcas Jaramillo <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Polit\u00e9cnica de catalunya<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 19\/09\/2011<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Alejandro Ram\u00edrez Bellido<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: eduard Ayguad\u00e9 parra <\/li>\n<li>osman Unsal Garc\u00eda (vocal)<\/li>\n<li>georgi Nedeltchev gaydadjiev (vocal)<\/li>\n<li>miquel Peric\u00ed\u00a0s gleim (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Felipe Cabarcas Jaramillo Debido a las mejoras tecnol\u00f3gicas y limitaciones en consumo de potencia de los microprocesadores, [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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