{"id":128832,"date":"1996-01-01T00:00:00","date_gmt":"1996-01-01T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/integracion-de-planificacion-temporal-y-asignacion-de-recursos-hardware-en-sintesis-de-alto-nivel\/"},"modified":"1996-01-01T00:00:00","modified_gmt":"1996-01-01T00:00:00","slug":"integracion-de-planificacion-temporal-y-asignacion-de-recursos-hardware-en-sintesis-de-alto-nivel","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/ciencias-tecnologicas\/integracion-de-planificacion-temporal-y-asignacion-de-recursos-hardware-en-sintesis-de-alto-nivel\/","title":{"rendered":"Integracion de planificacion temporal y asignacion de recursos hardware en sintesis de alto nivel."},"content":{"rendered":"<h2>Tesis doctoral de <strong>  Moreno Vozmediano Rafael Aurelio <\/strong><\/h2>\n<p>El objetivo fundamental de este proyecto investigador es el desarrollo de una metodolog\u00eda para la integracion de dos de las tareas fundamentales en sintesis de alto nivel: la planificacion temporal de operaciones y la asignacion de recursos hardware. Este trabajo esta enmarcado dentro de un proyecto mas amplio, denominado fidias, que tiene como finalidad el desarrollo de un entornio completo de dise\u00f1o automatico de circuitos integrados.  el metodo de planificacion y asignacion que se presenta, parte de un grafo de flujo de datos sin planificar (traduccion directa de la descripcion algoritmica del circuito a dise\u00f1ar), una biblioteca real de modulos hardware, el tiempo de ciclo decidido por un modulo de control del dise\u00f1o y las restricciones de area y tiempo dadas por el usuario. A partir de estas entradas, se realiza una asignacion simultanea de operaciones a etapas de control y a unidades funcionales, con el objetivo de encontrar una o varias soluciones de bajo coste de area, para un numero de etapas de control fijo impuesto por la restriccion temporal.  en la metodolog\u00eda propuesta se realiza una exploracion guiada del espacio de dise\u00f1o, cuyas principales decisiones se basan en el analisis global de la estructura del grafo de flujo de datos y las caracteristicas de la biblioteca de modulos y en la estimacion de costes de los dise\u00f1os parciales.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Integracion de planificacion temporal y asignacion de recursos hardware en sintesis de alto nivel.<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Integracion de planificacion temporal y asignacion de recursos hardware en sintesis de alto nivel. <\/li>\n<li><strong>Autor:<\/strong>\u00a0  Moreno Vozmediano Rafael Aurelio <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Complutense de Madrid<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 01\/01\/1996<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Roman Hermida Correa<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Francisco Tirado Fern\u00e1ndez <\/li>\n<li> Lopez Lopez Juan  Carlos (vocal)<\/li>\n<li>Antonio Nu\u00f1ez Ordo\u00f1ez (vocal)<\/li>\n<li>Eugenio Villar Bonet (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Moreno Vozmediano Rafael Aurelio El objetivo fundamental de este proyecto investigador es el desarrollo de una metodolog\u00eda [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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