{"id":131631,"date":"1996-01-01T00:00:00","date_gmt":"1996-01-01T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/diseno-formal-orientado-a-hardware-de-sistemas-telematicos-de-lotos-a-vhdl\/"},"modified":"1996-01-01T00:00:00","modified_gmt":"1996-01-01T00:00:00","slug":"diseno-formal-orientado-a-hardware-de-sistemas-telematicos-de-lotos-a-vhdl","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/ciencias-tecnologicas\/diseno-formal-orientado-a-hardware-de-sistemas-telematicos-de-lotos-a-vhdl\/","title":{"rendered":"Dise\u00f1o formal orientado a hardware de sistemas telematicos: de lotos a vhdl."},"content":{"rendered":"<h2>Tesis doctoral de <strong> Andres Marin Lopez <\/strong><\/h2>\n<p>En esta tesis se propone el uso de una metodolog\u00eda basada en los lenguajes lotos y vhdl y en herramientas de dise\u00f1o automaticas para el dise\u00f1o de sistemas tellematicas y aplicaciones orientadas a control. La metodolog\u00eda propone realizar especificaciones mediante refinamientos sucesivos. Dichas especificaciones han de ser validadas con respecto a una especificacion formal de requisitos del sistema. Las implementaciones en vhdl sintetizable se obtienen por traduccion automatica. La traduccion se demuestra que es correcta siempre de forma que no es preciso verificarla en cada dise\u00f1o. A partir de esta descripcion vhdl se utilizan las herramientas de sintesis automaticas.  en el desarrollo de esta tesis se describe la traduccion de lotos a vhdl y la demostracion formal de que es correcta. Debido al gran numero de demostraciones intermedias que comporta esta demostracion, se decide implementar las semanticas de ambos lenguajes, de la traduccion y de la funcion de correspondencia de estados vhdl a estados lotos en un lenguaje funcional de evaluacion perezoso llamado gofer. Todas las demostraciones son automatizables en gofer.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Dise\u00f1o formal orientado a hardware de sistemas telematicos: de lotos a vhdl.<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Dise\u00f1o formal orientado a hardware de sistemas telematicos: de lotos a vhdl. <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Andres Marin Lopez <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Polit\u00e9cnica de Madrid<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 01\/01\/1996<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Carlos Delgado Kloos<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal:  Miguel Moro Tomas De <\/li>\n<li>Jaime Ruz Jose (vocal)<\/li>\n<li>Roman Hermida Correa (vocal)<\/li>\n<li>Eugenio Villar Bonet (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Andres Marin Lopez En esta tesis se propone el uso de una metodolog\u00eda basada en los lenguajes [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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