{"id":18417,"date":"2002-12-07T00:00:00","date_gmt":"2002-12-07T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/high-performance-instruction-fetch-using-software-and-hardware-co-desing\/"},"modified":"2002-12-07T00:00:00","modified_gmt":"2002-12-07T00:00:00","slug":"high-performance-instruction-fetch-using-software-and-hardware-co-desing","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/matematicas\/high-performance-instruction-fetch-using-software-and-hardware-co-desing\/","title":{"rendered":"High performance instruction fetch using software and hardware co-desing"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Alejandro Ram\u00edrez Bellido <\/strong><\/h2>\n<p>En los \u00faltimos a\u00f1os, el dise\u00f1o de procesadores de altas prestaciones ha progresado a lo largo de dos corrientes de investigaci\u00f3n: incrementar la profundidad del pipeline para permitir mayores frecuencias de reloj, y ensanchar el pipeline para permitir la ejecucci\u00f3n paralela de un mayor n\u00famero de instrucciones. Dise\u00f1ar un procesador de altas prestaciones implica balancear todos los componentes del procesador para asegurar que el rendimiento global no esta limitado por ning\u00fan componente individual. Esto quiere decir que si dotamos al procesador de una unidad de ejecuci\u00f3n m\u00e1s r\u00e1pida, hay que asegurarse de que podemos hacer fetch y decodificar instrucciones a una velocidad suficiente para mantener ocupada a esa unidad de ejecuci\u00f3n.  esta tesis explora los retos presentados por el dise\u00f1o de la unidad de fetch desde dos puntos de vista: el dise\u00f1o de un software mas adecuado para las arquitecturas de fetch ya existentes, y el dise\u00f1o de un hardware adaptado a las caracter\u00edsticas especiales del nuevo software que hemos generado.  nuestra aproximaci\u00f3n al dise\u00f1o de un suevo software ha sido la propuesta de un nuevo algoritmo de reordenaci\u00f3n de c\u00f3digo que no solo pretende mejorar el rendimiento de la cache de instrucciones, sino que al mismo tiempo pretende incrementar la anchura efectiva de la unidad de fetch. Usando informaci\u00f3n sobre el comportamiento del programa (profile data), encadenamos los bloques b\u00e1sicos del programa de forma que los saltos condicionales tendr\u00e1n tendencia a ser no tomados, lo cual favorece la ejecucci\u00f3n secuencial del c\u00f3digo. una vez hemos organizado los bloques b\u00e1sicos en estas trazas, mapeamos las diferentes trazas en memoria de forma que minimicen la cantidad de espacio requerida para el c\u00f3digo realmente \u00fatil, y los conflictos en memoria de este c\u00f3digo. Adem\u00e1s de describir el algoritmo, hemos realizado un an\u00e1lisis en detalle del impacto de estas optimizaciones sobre los diferentes aspectos<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>High performance instruction fetch using software and hardware co-desing<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 High performance instruction fetch using software and hardware co-desing <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Alejandro Ram\u00edrez Bellido <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Polit\u00e9cnica de catalunya<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 12\/07\/2002<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li> Larriba Pey Jos\u00e9 Luis<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Jes\u00fas jos\u00e9 Labarta mancho <\/li>\n<li>Ana Mar\u00eda Ripoll aracil (vocal)<\/li>\n<li>richard Kaeli david (vocal)<\/li>\n<li>Emilio Luque fadon (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Alejandro Ram\u00edrez Bellido En los \u00faltimos a\u00f1os, el dise\u00f1o de procesadores de altas prestaciones ha progresado a [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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