{"id":31362,"date":"1997-01-01T00:00:00","date_gmt":"1997-01-01T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/symbolic-analysis-of-switch-level-circuits\/"},"modified":"1997-01-01T00:00:00","modified_gmt":"1997-01-01T00:00:00","slug":"symbolic-analysis-of-switch-level-circuits","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/ciencias-tecnologicas\/symbolic-analysis-of-switch-level-circuits\/","title":{"rendered":"Symbolic analysis of switch-level circuits."},"content":{"rendered":"<h2>Tesis doctoral de <strong> LLuis Ribas Xirgo <\/strong><\/h2>\n<p>La verificacion de circuitos mediante tecnicas simbolicas permite reducir el numero de pasos hacia dise\u00f1os correctos. Estas mismas tecnicas pueden complementar soluciones convencionales en la generacion y validacion de patrones de test para los circuitos dise\u00f1ados. En este trabajo se ha creado un entorno matematico que permite el modelado de circuitos a nivel de transistor y asegura la validez de los resultados de algoritmos dirigidos por eventos que se utilizan para analizar los circuitos.  en particular, se ha relacionado una algebra booleana de funciones de cuatro valores con la representacion de los caminos electricos desde los nodos de un circuito hasta el de alimentacion y el de tierra. Las dos clases de caminos se representan individualmente a traves de dos funciones definidas en una algebra de dos valores y se obtienen a traves de una simulacion simbolica dirigida por eventos. Finalmente, se ha realizado el programa correspondiente (symsim) y se ofrece una metodolog\u00eda completa para la comprobacion de estas funciones asociadas a los nodos de los circuitos, asi como una aproximacion a la generacion de vectores de test en la que, ademas, se describe un algoritmo para su compactado.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Symbolic analysis of switch-level circuits.<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Symbolic analysis of switch-level circuits. <\/li>\n<li><strong>Autor:<\/strong>\u00a0 LLuis Ribas Xirgo <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Aut\u00f3noma de barcelona<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 01\/01\/1997<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Jordi Carrabina Bordoll<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Jordi Aguico Llobet <\/li>\n<li>Jordi Cortadella Fortuny (vocal)<\/li>\n<li>Roman Hermida Correa (vocal)<\/li>\n<li>LLuis Teres Teres (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de LLuis Ribas Xirgo La verificacion de circuitos mediante tecnicas simbolicas permite reducir el numero de pasos hacia [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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