{"id":36170,"date":"1998-01-01T00:00:00","date_gmt":"1998-01-01T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/gestion-multinivel-y-prebusqueda-hardware-en-memorias-cache-integradas\/"},"modified":"1998-01-01T00:00:00","modified_gmt":"1998-01-01T00:00:00","slug":"gestion-multinivel-y-prebusqueda-hardware-en-memorias-cache-integradas","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/matematicas\/gestion-multinivel-y-prebusqueda-hardware-en-memorias-cache-integradas\/","title":{"rendered":"Gestion multinivel y prebusqueda hardware en memorias cache integradas."},"content":{"rendered":"<h2>Tesis doctoral de <strong> Pablo Enrique Iba\u00f1ez Mar\u00edn <\/strong><\/h2>\n<p>En esta tesis se estudian dos soluciones para minimizar el impacto de la latencia en las prestaciones de un procesador con caches integradas. Las dos soluciones act\u00faan sobre el sistema de memoria para reducir bien el n\u00famero de fallos, bien su latencia.  en primer lugar se estudia la incorporaci\u00f3n de varios niveles de cache dentro del chip del procesador. El objetivo de esta soluci\u00f3n es disminuir la penalizaci\u00f3n media sufrida por un fallo en el primer nivel de la jerarqu\u00eda. El hecho de implementar dos niveles de cache muy acoplados crea nuevas condiciones de contorno, aparecen nuevas posibilidades y tambi\u00e9n nuevos compromisos. Se estudia la relaci\u00f3n de contenidos entre los dos niveles integrados. Se compara la gesti\u00f3n convencional en inclusi\u00f3n con nuevos m\u00e9todos de gesti\u00f3n en exclusi\u00f3n y demanda.  en segundo lugar se estudia la incorporaci\u00f3n de mecanismos de preb\u00fasqueda hardware de datos. El objetivo de esta soluci\u00f3n es disminuir el n\u00famero de fallos en las caches m\u00e1s cercanas al procesador. Entre los m\u00e9todos existentes se seleccionan los m\u00e1s apropiados para caches integradas y se analiza su coste y rendimiento. Tras este an\u00e1lisis se proponen dos nuevos mecanismos de bajo coste que consiguen prestaciones similares a las de los mecanismos convencionales.  durante todo el desarrollo de la tesis, y en paralelo con el trabajo central, se ha prestado especial atenci\u00f3n al desarrollo de t\u00e9cnicas para la disminuci\u00f3n del coste temporal de simulaci\u00f3n. Se han depurado para ello nuevas t\u00e9cnicas de muestreo temporal aplicables a simuladores ciclo a ciclo en un contexto general de procesadores y jerarqu\u00edas de memoria con elevada actividad paralela.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Gestion multinivel y prebusqueda hardware en memorias cache integradas.<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Gestion multinivel y prebusqueda hardware en memorias cache integradas. <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Pablo Enrique Iba\u00f1ez Mar\u00edn <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Zaragoza<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 01\/01\/1998<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Victor Vi\u00f1als Yufera<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Jos\u00e9 Mar\u00eda Llaberia Gri\u00f1\u00f3 <\/li>\n<li>Clemente Rodriguez Lafuente (vocal)<\/li>\n<li>Julio Ramon Beivide Palacio (vocal)<\/li>\n<li> Olive I Duran Angel (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Pablo Enrique Iba\u00f1ez Mar\u00edn En esta tesis se estudian dos soluciones para minimizar el impacto de la [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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