{"id":60194,"date":"2018-03-09T22:48:00","date_gmt":"2018-03-09T22:48:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/design-techniques-for-filly-integrated-cmos-power-amplifiers-applied-to-the-ieee-802-11a-standard\/"},"modified":"2018-03-09T22:48:00","modified_gmt":"2018-03-09T22:48:00","slug":"design-techniques-for-filly-integrated-cmos-power-amplifiers-applied-to-the-ieee-802-11a-standard","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/radiocomunicaciones\/design-techniques-for-filly-integrated-cmos-power-amplifiers-applied-to-the-ieee-802-11a-standard\/","title":{"rendered":"Design techniques for filly integrated cmos power amplifiers applied to the ieee 802.11a standard"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Juan Melendez Lagunilla <\/strong><\/h2>\n<p>#titulo: design techniques for fully integrated cmos power amplifiers applied to the ieee 802.11a standard #resumen: la gran difusi\u00f3n de los sistemas inal\u00e1mbricos que se observa actualmente refleja el inter\u00e9s del mercado por una mayor conectividad. Las personas quieren la informaci\u00f3n aqu\u00ed y ahora, y no aceptan ninguna limitaci\u00f3n de espacio o tiempo. La demanda del mercado lleva, por tanto, al desarrollo de dispositivos port\u00e1tiles que sean capaces de conectarse a las tecnolog\u00edas inal\u00e1mbricas emergentes: ordenadores port\u00e1tiles, tel\u00e9fonos m\u00f3viles o agendas electr\u00f3nicas necesitan ofrecer caracter\u00edsticas de conectividad extras que van m\u00e1s all\u00e1 de sus aplicaciones originales. De esta manera, esos dispositivos deben reducir no s\u00f3lo sus consumos de potencia, sino tambi\u00e9n las dimensiones de sus componentes electr\u00f3nicos. En otras palabras, los circuitos integrados de radiofrecuencia (rf \u00edes) de alto rendimiento, bajo coste y alta integrabilidad son cada vez m\u00e1s demandados por la industria de la electr\u00f3nica de consumo. Sin embargo, todav\u00eda existe un componente de radiofrecuencia que sigue reacio a ser integrado: el amplificador de potencia (pa). El pa ha sido siempre el cuello de botella, en lo que respecta a los circuitos integrados de radiofrecuencia, debido al compromiso existente entre las caracter\u00edsticas de alto rendimiento y alta integrabilidad. Si se requieren pas de alto rendimiento, los dise\u00f1adores se centran en procesos basados en asga que resultan muy caros y, adem\u00e1s, impiden integrar el pa en dispositivos de bajo precio y alta integrabilidad. Al rev\u00e9s, si desea una alta integraci\u00f3n, \u00e9stos f\u00e1cilmente renuncian a obtener componentes de alto rendimiento. Por lo tanto, los pas implementados en procesos cmos est\u00e1ndar que a la vez que ofrezcan rendimientos cercanos a los basados en procesos de asga son muy atractivos, porque los procesos cmos est\u00e1n siendo actualmente muy usados en dise\u00f1os de circuitos integrados de radiofrecuencia y porque los pas basados en cmos son de bajo coste y alta integrabilidad. Este trabajo de investigaci\u00f3n se centra, por tanto, en las t\u00e9cnicas de dise\u00f1o de pas completamente integrados y basados en procesos cmos para las tecnolog\u00edas inal\u00e1mbricas, concretamente, el est\u00e1ndar 802.11a. Este est\u00e1ndar opera a 5 ghz y complementa a los est\u00e1ndares 802.11b y .Llg que operan a 2.4 ghz. Estos tres est\u00e1ndares disfrutan de una gran penetraci\u00f3n en el mercado y trabajan con niveles medios de potencia dando una cobertura local. De esta manera, el est\u00e1ndar 802.11a es un buen candidato para este trabajo de investigaci\u00f3n. La metodolog\u00eda de dise\u00f1o comienza con el estudio del est\u00e1ndar para fijar los requerimientos del pa. Los componentes pasivos han sido cuidadosamente dise\u00f1ados. Se ha puesto especial atenci\u00f3n a los inductores ya que son los componentes cr\u00edticos para el rendimiento de todo el pa. Posteriormente, se ha llevado a cabo el dise\u00f1o del circuito integrado realizando un estudio previo de la arquitectura m\u00e1s adecuada para el mismo. Las herramientas software utilizadas para el dise\u00f1o han sido ads de agilent y virtuoso de cadence. Despu\u00e9s, bas\u00e1ndose en el punto de partida facilitado por un nuevo modelo desarrollado en este trabajo, se han realizado las simulaciones postlayout utilizando spectrerf de cadence. Finalmente, el pa ha sido fabricado y medido con el fin de validar el circuito y el modelo desarrollado. Los resultados muestran la viabilidad de los pas basados en procesos cmos para aplicaciones de alta frecuencia y niveles de potencia medios. Demuestran, adem\u00e1s, que los pas de bajo coste pueden ser una buena alternativa a los pas basados en los procesos gaas de alto precio.   the great spread of wireless systems that can be now observed reflects the interest of the market for a greater connectivity. People require information here and now and do not accept any limitation of place or time. The demand of the market leads then to the development of portable devices able to connect to the emerging wireless technologies: laptops, cellular phones or pdas (personal digital assistants) need to offer extra connectivity functions beyond their initial applications. Therefore, those devices must further reduce not only their power consumption but also the size of their electronics. In other words, high performance, low cost and highly integrated radio frequency integrated circuits (rf \u00edes) are increasingly required from the consumer electronics industry. However, there is still a rf component that remains reluctant to be integrated: the power amplifier (pa). The pa has been always a bottleneck regarding radio frequency integrated circuits (rf \u00edes) due to tne exist\u00ed\u00bbng tradeoff between high-performance and high integration characteristics. If high-performance pas are required, designers focus on expensive gaas processes that prevent pas from being implemented in low cost, highly integrated devices. Conversely, if high integration is desired, designers easily resign from achieving high-performance components. Therefore, pas implemented in standard cmos processes while offering performances ci\u00f3se to those found in gaas ones are highly attractive because cmos processes are nowadays extensively used in rf \u00edes implementations and because cmos pas offer low cost and high integration characteristics. This work focuses then on the design techniques of fully integrated cmos pas for wireless applications, concrete!Y, for the 802.11a standard. This standard operates at 5 ghz and complements the 802.11b and .Llg wlan standards, found at 2.4 ghz. These standards enjoy and outstanding market penetration while offering medium transmit power leveis and local area coverage and, therefore, the 802.11a is a good candi date for this research project. The design methodology starts with a study of the standard in order to set the requirements of the pa. The passive elements, with special attention to the inductors, which are critical for the pa performance, nave been carefully designed. Then, the design of the ic has been carried out with a previous study of the most suitable architecture for the pa. Advanced design system (ads) of agilent and virtuoso of cadence have been the chosen software tools to perform the overall design. After that, based on a starting point obtained from a new developed model, spectrerf of cadenee has been used for the schematic and postlayout simulations. Finally, the pa has been fabricated and measured in order to validate the device and the proposed model. Experimental results show the viability of the cmos power amplifiers for high frequeney, m\u00e9dium power wireless applications and dem\u00f3nstrate that \u00ablow cost pas can be a good alternative to expensive gaas pas.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Design techniques for filly integrated cmos power amplifiers applied to the ieee 802.11a standard<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Design techniques for filly integrated cmos power amplifiers applied to the ieee 802.11a standard <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Juan Melendez Lagunilla <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Navarra<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 23\/07\/2007<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Roque Jose Berenguer Perez<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: pedro Crespo bofill <\/li>\n<li>Jorge Presa alonso (vocal)<\/li>\n<li>c\u00e9sar Sanz alvaro (vocal)<\/li>\n<li>domingo Jos\u00e9 Miguel De diego rodrigo (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Juan Melendez Lagunilla #titulo: design techniques for fully integrated cmos power amplifiers applied to the ieee 802.11a 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