{"id":70706,"date":"2004-08-10T00:00:00","date_gmt":"2004-08-10T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/evaluacion-de-arquitecturas-integradas-en-procesadores\/"},"modified":"2004-08-10T00:00:00","modified_gmt":"2004-08-10T00:00:00","slug":"evaluacion-de-arquitecturas-integradas-en-procesadores","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/matematicas\/evaluacion-de-arquitecturas-integradas-en-procesadores\/","title":{"rendered":"Evaluaci\u00f3n de arquitecturas integradas en procesadores"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Rafael Rico L\u00f3pez <\/strong><\/h2>\n<p>En el \u00e1mbito de la concurrencia de grano fino han sido identificados diferentes factores limitantes del paralelismo que las arquitecturas integradas en procesadores m\u00e1s recientes intentan eludir.En el presente trabajo se parte de la hip\u00f3tesis de que el propio repertorio de instrucciones tiene un impacto decisivo en este sentido.  la demostraci\u00f3n se ha realizado utilizando una cuantificaci\u00f3n del grado de paralelismo basada en el grafo de dependiencias de datos que es novedosa a la vez que independiente de la implantaci\u00f3n f\u00edsica.Se ha realizado una validaci\u00f3n de esta t\u00e9cnica , comp\u00e1randola con medidas basadas en tiempo que son m\u00e1s tradicionales y aceptadas y se ha construido un simulador basado en traza parametrizable adecuado al caso.  como resultado se concluye que efectivamente los accesos a operandos impl\u00edcitos derivados de la arquitectura del repertorio de instrucciones y m\u00e1s concretamente , los derivados del registro de estado, afectan negativamente al grado de concurrencia habi\u00e9ndose determinado una posible mejora para el banco de pruebas utilizado en torno al 10% si se elude esta circunstancia.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Evaluaci\u00f3n de arquitecturas integradas en procesadores<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Evaluaci\u00f3n de arquitecturas integradas en procesadores <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Rafael Rico L\u00f3pez <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Complutense de Madrid<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 08\/10\/2004<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Daniel Meziat Luna<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Antonio Hernandez cachero <\/li>\n<li>Juan  Manuel S\u00e1nchez p\u00e9rez (vocal)<\/li>\n<li>ramon Puigtjaner trepat (vocal)<\/li>\n<li>eduard Montseny masip (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Rafael Rico L\u00f3pez En el \u00e1mbito de la concurrencia de grano fino han sido identificados diferentes factores [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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