{"id":75985,"date":"2018-03-09T23:21:19","date_gmt":"2018-03-09T23:21:19","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/metodologa%c2%ada-de-diseno-de-sistemas-digitales-para-telecomunicaciones-basada-en-c-c-aplicacion-a-wlan-802-11a\/"},"modified":"2018-03-09T23:21:19","modified_gmt":"2018-03-09T23:21:19","slug":"metodologa%c2%ada-de-diseno-de-sistemas-digitales-para-telecomunicaciones-basada-en-c-c-aplicacion-a-wlan-802-11a","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/radiocomunicaciones\/metodologa%c2%ada-de-diseno-de-sistemas-digitales-para-telecomunicaciones-basada-en-c-c-aplicacion-a-wlan-802-11a\/","title":{"rendered":"Metodolog\u00eda de dise\u00f1o de sistemas digitales para telecomunicaciones basada en c\/c++: aplicaci\u00f3n a wlan 802.11a"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Igone Velez Isasmendi <\/strong><\/h2>\n<p>Titulo: metodolog\u00eda de dise\u00f1o de sistemas digitales para telecomunicaciones basada en c\/c++: aplicaci\u00f3n a wlan 802.Lla  resumen: en el competitivo mercado de las telecomunicaciones, la reducci\u00f3n de los tiempos de desarrollo de un nuevo producto es imprescindible para conseguir y mantener una posici\u00f3n estrat\u00e9gica. La norma es dise\u00f1ar aplicaciones para circuitos integrados compuestos de decenas de millones de transistores. Estos sistemas est\u00e1n formados por m\u00f3dulos de hardware complejos, integrados para crear un dise\u00f1o system-on-chip (soc). El dise\u00f1o de uno de estos sistemas requiere de varias fases de simulaci\u00f3n antes de la creaci\u00f3n del hardware, que pueden ser divididas en dos grupos dependiendo de en qu\u00e9 etapa se haya realizado la simulaci\u00f3n: evaluaci\u00f3n de la funcionalidad en una primera etapa y la validaci\u00f3n del hardware en una etapa posterior. Los grupos de dise\u00f1o precisan de herramientas de simulaci\u00f3n funcional m\u00e1s veloces y que, adem\u00e1s, faciliten el dise\u00f1o de la arquitectura del sistema. Dichas herramientas deber\u00e1n permitir una r\u00e1pida verificaci\u00f3n del sistema. Asimismo, deber\u00e1n ser simples de utilizar, con una curva de aprendizaje reducida. En los \u00faltimos a\u00f1os, las compa\u00f1\u00edas desarrolladoras de herramientas de dise\u00f1o hardware est\u00e1n realizando un gran esfuerzo para responder a los requerimientos de los grupos de dise\u00f1o. Por desgracia, estas herramientas, muchas veces, tienen unos costes prohibitivos para numerosas empresas. Con esta idea en mente, se propone una metodolog\u00eda de trabajo basada en una nueva herramienta denominada harbest. Este novedoso entorno de desarrollo trata de responder a las necesidades de los grupos de dise\u00f1o, aunando la etapa de descripci\u00f3n funcional y arquitectural en una \u00fanica y acelerando la verificaci\u00f3n del sistema, mediante la reutilizaci\u00f3n de los vectores de test empleados. Harbest est\u00e1 basado en el lenguaje c\/c++, lo que facilita el aprendizaje de la herramienta. Para simplificar aun m\u00e1s su   uso, se le ha dotado de una interfaz gr\u00e1fica. Adem\u00e1s, harbest requiere \u00fanicamente de herramientas no propietarias, con la consecuente reducci\u00f3n en costes. Se ha empleado esta nueva metodolog\u00eda en el dise\u00f1o del procesador de banda base de ieee 802.11a para wlan. Primeramente, se ha aplicado dicha metodolog\u00eda al an\u00e1lisis del sistema. Esto permite determinar en una etapa temprana del proyecto tanto la arquitectura del sistema como diversos par\u00e1metros relacionados con la implementaci\u00f3n, tales como la frecuencia de reloj, los tiempos de operaci\u00f3n, los efectos de cuantizaci\u00f3n, etc..  Posteriormente, se aplica esta metodolog\u00eda al dise\u00f1o de bloques aritm\u00e9ticos y de control. Como ejemplo del primer tipo de m\u00f3dulos, se dise\u00f1a una ifft\/fft que cumpla con las especificaciones del est\u00e1ndar 802.11a. Se comprueba que harbest es una herramienta \u00fatil para el dise\u00f1o de bloques aritm\u00e9ticos, ya que permite trabajar con varias vistas de un mismo m\u00f3dulo, lo que facilita la determinaci\u00f3n de la arquitectura \u00f3ptima y el dimensionado del tama\u00f1o de los datos. Como ejemplo del dise\u00f1o de m\u00f3dulos de control, se desarrolla un microprocesador que realice las funciones de la subcapa plcp de dicho est\u00e1ndar. De este ejemplo, se concluye que harbest es una herramienta que facilita el codise\u00f1o hardware-software. Finalmente, se ha sintetizado el procesador implementado tanto en un asic como en una fpga. Asimismo, se ha prototipado el transmisor, comprobando que cumple las especificaciones del standard ieee 802.11a.  lf a company wants to achieve and maintain a strategic position in the competitive market of telecommunications, it should try to reduce the development time of their new products. Nowadays integrated circuits contain millions of transistors. These systems are composed of complex hardware modules that are integrated to create a system-on-chip (soc) design. The development of one of these systems requires various phases of simulations before the hardware is developed. In a first stage the functionality is evaluated and in a second stage the hardware must be validated. Design groups need quicker functional simulation tools that simplify the design of the system architecture. Besides, these tools should allow the user to verify rapidly the system. Additionally, they must be easy to use, with a reduced learning curve, in the last years, eda companies are making an effort to answer to the requirements of hardware design groups. Unfortunately, these tools usually have prohibitive priees. Bearing this idea in mind, a new methodology has been proposed, which is based on a novel tool called harbest. This development environment answers to the necessities of design groups, joining the functional and the architectural description stage. It will accel\u00e9rate the system verificati\u00f3n, by reusing of testbenches. Harbest is based on the well-known c\/c++ language, which speeds-up the learning of the tool. Harbest has a graphical interface that simplifies even more its use. Besides, harbest works with non-proprietary tools, henee reducing its costs. We have employed this new methodology in the design of the ieee 802.11a baseband processor for wlan. Firstly, this methodology has been applied to analyze the system. This way, the architecture of the system and some parameters related with the imp\u00edementation, such as the clock frequeney, operating time, quantization effeets, etc&#8230;, Were set at a early stage of the project. Later on, this methodology is applied to the design of arithmetical and control blocks. As an example of the first kind of modules, an ifft\/fft has been designed that satisfies the specifications of the standard 802.11a. Harbest is a useful tool for the design of arithmetical blocks, as it allows the designer to work with different views of the same module. This makes it easier to determine the optimal architecture and to dimensi\u00f3n word lengths. As an example of the design of a control module, a microprocessor has been developed. This microprocessor carries out the functionality of the plcp sub\u00edayer of the ieee 802.11a standard, we conclude that harbest is a tool that simplifies the hardware-software codesign. Finally, the implemented baseband processor has been synthesized for an asic and a fpga. Moreover, the transmitter has been prototyped, verifying that it fulfils the requirements of the standard ieee 802.Lia<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Metodolog\u00eda de dise\u00f1o de sistemas digitales para telecomunicaciones basada en c\/c++: aplicaci\u00f3n a wlan 802.11a<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Metodolog\u00eda de dise\u00f1o de sistemas digitales para telecomunicaciones basada en c\/c++: aplicaci\u00f3n a wlan 802.11a <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Igone Velez Isasmendi <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Navarra<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 22\/07\/2005<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Andoni Irizar Picon<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: manuel Fuentes perez <\/li>\n<li>teresa Riesgo alcalde (vocal)<\/li>\n<li>jon Altuna iraola (vocal)<\/li>\n<li>Javier Hern\u00e1ndez de Miguel (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Igone Velez Isasmendi Titulo: metodolog\u00eda de dise\u00f1o de sistemas digitales para telecomunicaciones basada en c\/c++: aplicaci\u00f3n a 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