{"id":77492,"date":"2018-03-09T23:23:01","date_gmt":"2018-03-09T23:23:01","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/diseno-de-circuitos-con-protocolos-de-sincronizacion-self-timed-en-dispositivos-programales-fpgas\/"},"modified":"2018-03-09T23:23:01","modified_gmt":"2018-03-09T23:23:01","slug":"diseno-de-circuitos-con-protocolos-de-sincronizacion-self-timed-en-dispositivos-programales-fpgas","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/fisica\/diseno-de-circuitos-con-protocolos-de-sincronizacion-self-timed-en-dispositivos-programales-fpgas\/","title":{"rendered":"Dise\u00f1o de circuitos con protocolos de sincronizacion self timed en dispositivos programales fpgas"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Susana Ortega Cisneros <\/strong><\/h2>\n<p>En esta tesis se presenta el dise\u00f1o e implementaci\u00f3n de circuitos digitales con sincronizaci\u00f3n self-timed (st). Se desarrolla una metodolog\u00eda para el prototipado r\u00e1pido de circuitos con sincronizaci\u00f3n st en fpgas como una alternativa de bajo coste y tiempo  de dise\u00f1o.  los circuitos desarrollados en este trabajo as\u00ed, como la descripci\u00f3n de los m\u00f3dulos de control y bloques de procesamiento, est\u00e1n basados en estructuras micropipeline st de 2 y 4 fases. \u00e9stas se utilizan para el control de circuitos aritm\u00e9ticos, redes neuronales y microprocesadores. Se propone una metodolog\u00eda para la implementaci\u00f3n de retardos en fpgas y se aborda en detalle el dise\u00f1o de los bloques de control as\u00edncronos (bcas). Adem\u00e1s se presentan las propuestas y an\u00e1lisis de circuitos de control as\u00edncronos distribuidos y centralizados para la optimizaci\u00f3n de los recursos disponibles en las fpgas.  finalmente se describe el dise\u00f1o de los m\u00f3dulos que componen a un microprocesador st de 16 bits, desarrollado con un protocolo de 4 fases, que s\u00f3lo requiere de un pulso externo a la entrada para iniciar el proceso de ejecuci\u00f3n de las instrucciones, el cual presenta una mejora de consumo de potencia con respecto a su homologo s\u00edncrono.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Dise\u00f1o de circuitos con protocolos de sincronizacion self timed en dispositivos programales fpgas<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Dise\u00f1o de circuitos con protocolos de sincronizacion self timed en dispositivos programales fpgas <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Susana Ortega Cisneros <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Aut\u00f3noma de Madrid<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 30\/11\/2005<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Eduardo Boemo Scalvinoni<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: javier Garrido salas <\/li>\n<li>sergio Cuenca asesi (vocal)<\/li>\n<li> Gomez arrivas  Francisco Javier (vocal)<\/li>\n<li>Juan Suardias muro (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Susana Ortega Cisneros En esta tesis se presenta el dise\u00f1o e implementaci\u00f3n de circuitos digitales con sincronizaci\u00f3n [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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