{"id":77505,"date":"2018-03-09T23:23:01","date_gmt":"2018-03-09T23:23:01","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/reconfigurable-architectures-for-sigma-delta-analog-to-digital-converters-in-low-voltage-low-power-transceivers\/"},"modified":"2018-03-09T23:23:01","modified_gmt":"2018-03-09T23:23:01","slug":"reconfigurable-architectures-for-sigma-delta-analog-to-digital-converters-in-low-voltage-low-power-transceivers","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/radiocomunicaciones\/reconfigurable-architectures-for-sigma-delta-analog-to-digital-converters-in-low-voltage-low-power-transceivers\/","title":{"rendered":"Reconfigurable architectures for sigma delta analog to digital converters in low voltage low power transceivers"},"content":{"rendered":"

Tesis doctoral de Santiago Ricardo Urquijo Tardio <\/strong><\/h2>\n

Titulo: reconfigurable architectures for sigma delta analog to digital converters in low voltage low power transceivers el objetivo de la tesis es el estudio de arquitecturas (de tiempo discreto) sigma delta para convertidores anal\u00f3gico digital (adc) de baja tensi\u00f3n de alimentaci\u00f3n en receptores de telecomunicaciones de bajo consumo de potencia. Dentro de los requerimientos de la topolog\u00eda destaca el bajo nivel de tensi\u00f3n de alimentaci\u00f3n, la eficiencia de potencia, el requerimiento de un n\u00famero m\u00ednimo de componentes externos y la ausencia de calibraci\u00f3n. Para poder validar la investigaci\u00f3n, ha sido implementada una arquitectura sigma delta en la tecnolog\u00eda 0.35 um 2p3m cmos de ams. El convertidor forma parte de un receptor ism de 403 mhz, que requiere dos adcs para los canales i y q. El convertidor emplea un reloj de frecuencia 3.84 mhz y una tensi\u00f3n de alimentaci\u00f3n de 1.8 v. El adc no necesita calibraci\u00f3n en ning\u00fan momento.La estrategia m\u00e1s empleada para reducir el consumo de potencia en convertidores anal\u00f3gico digital es la optimizaci\u00f3n de los diferentes componentes o la reducci\u00f3n del valor de las capacidades de acuerdo a las especificaciones del sistema. La operaci\u00f3n bajo una fuente de alimentaci\u00f3n de baja tensi\u00f3n dificulta a\u00fan m\u00e1s la implementaci\u00f3n. En la mayor\u00eda de las aplicaciones el adc opera con la m\u00e1xima resoluci\u00f3n, la cual es implementada de acuerdo a los requerimientos definidos para el peor caso posible. Sin embargo en muchos de los posibles escenarios pueden no ser necesaria esa (m\u00e1xima) resoluci\u00f3n definida para el peor caso (que adem\u00e1s define el consumo m\u00e1ximo de potencia). El convertidor pasa baja sigma delta implementado, dise\u00f1ado para minimizar los componentes externos y adem\u00e1s presentar un bajo consumo de potencia presenta una topolog\u00eda capaz de ser controlada por un procesador digital. El procesador adapta el orden del convertidor incrementando o decrementando la resoluci\u00f3n en funci\u00f3n de la resoluci\u00f3n requerida en cada momento. De esta manera el consumo de potencia var\u00eda de acuerdo con los requerimientos del sistema y la eficiencia final de potencia mejora. La arquitectura \u00abcascade\u00bb de moduladores un bit de primer orden mostr\u00f3 una gran estabilidad y una gran lineal i dad con un factor de sobremuestreo muy bajo (osr=12.8). La topolog\u00eda seleccionada permite tres configuraciones (alta, media y baja resoluci\u00f3n). Las medidas de laboratorio confirman las predicciones de los modelos a nivel de transistor y \u00abpot-layout\u00bb. El chip fabricado, que incluye dos adcs para las se\u00f1ales i y q, muestra 55.3 db, 43.7 db y 33.2 db de sndr en 150 khz de ancho de banda. El sndr para 30 khz es 70 db y el sfdr con 100 khz de banda es 82 db. El consumo de potencia de un adc a 1.8 v y 3.84 mhz es 4.64 mw. Los convertidores fueron dise\u00f1ados para poder operar a una tensi\u00f3n de alimentaci\u00f3n muy baja, las medidas de laboratorio muestran que el adc alcanza 60.09 db @ 120 khz a 1.25 v de alimentaci\u00f3n (frecuencia de muestreo 3.84 mhz ). El consumo de potencia de un convertidor a 1.25 v era de 763 uw. The objective of the thesis is the study of discrete time low power low pass sigma delta analog to digital architectures for low voltage and low power transceivers. Within the requirements of the topology outline the low voltage operation, the power efficieney, the requirement of the minimal external components and the absence of calibration. M order to vali date the research, a sigma delta architecture was fabricated using the 0.35 um 2p3m cmos-technology provided by ams. This converter is part of a 403 mhz ism band transceiver, which requires two adc converters for the i and q signal paths. The adc operates with a clock frequeney of 3.84 mhz and a voltage supply of 1.8 v. The adcs must not be calibrated. The most used strategy to decrease the power consumption in an analog-to-digital converter consists of the optimization of the different components or the reduction of the capacitor size according to the system specifications. The low voltage supply operation leads to more difficulties in the implementation. In most applications the adc always operates with the maximal resolution, which is designed according to the worst case system requirements. However, most scenarios may not require a permanent high resolution operation, which itself would demand maximal power consumption. A low pass sigma delta analog-to-digital converter, which is designed to require minimal external components and low power consumption, is presented. Related to resolution and power consumption, the topology selected, controlled by a digital processor, adapts their order to increase or decrease the aecuracy as a \u00edunction of the resolution required. Therefore the power consumption changes according to the requirements and the power efficieney is increased.The architecture of the converter is a cascade of first-order single bit modulators, which show high stability and high linearity at very low oversampling ratio (12.8). The selected converter topology permits three different configurations, which enables better power consumption performance. The different stages of the converter can be digitally activated or deactivated. This produces three different configurations with high, m\u00e9dium and low resolution. An external digital processor controls the configurations of the converter, so that the adc, according to the signal quality, consumes the minimal power and reduces the final power consumption. Jhe laboratory measurements confirm the results of the models, transistor level and post-layout simulations. The chip, which includes two adcs for the i and q signal paths, achieves in the different configurations 55.3 db, 43.7 db and 33.2 db at a 150 khz bandwidth. The sndr at 30 khz band is 70 db and the sfdr with 100 khz band is 82 db. The power consumption of one adc at 1.8 v and 3.84 mhz is 4.64 mw. The adc was also designed to op\u00e9rate with a \u00ablower voltage supply, the measurements show that the adc achieve 60.09 db @ 120 khz at 1.25 v @ 3.84 mhz sample-rate. The power consumption of one adc at 1.25 v was 763 uw.<\/p>\n

 <\/p>\n

Datos acad\u00e9micos de la tesis doctoral \u00abReconfigurable architectures for sigma delta analog to digital converters in low voltage low power transceivers<\/strong>\u00ab<\/h3>\n
    \n
  • T\u00edtulo de la tesis:<\/strong>\u00a0 Reconfigurable architectures for sigma delta analog to digital converters in low voltage low power transceivers <\/li>\n
  • Autor:<\/strong>\u00a0 Santiago Ricardo Urquijo Tardio <\/li>\n
  • Universidad:<\/strong>\u00a0 Navarra<\/li>\n
  • Fecha de lectura de la tesis:<\/strong>\u00a0 30\/11\/2005<\/li>\n<\/ul>\n

     <\/p>\n

    Direcci\u00f3n y tribunal<\/h3>\n
      \n
    • Director de la tesis<\/strong>\n
        \n
      • Fernando Aritzi Urquijo<\/li>\n<\/ul>\n<\/li>\n
      • Tribunal<\/strong>\n
          \n
        • Presidente del tribunal: pedro Crespo bofill <\/li>\n
        • gunter Rohmer (vocal)<\/li>\n
        • alfonso Carlosena Garc\u00eda (vocal)<\/li>\n
        • i\u00f1igo Unanue murguiondo (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

           <\/p>\n","protected":false},"excerpt":{"rendered":"

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