{"id":80923,"date":"2018-03-10T00:04:44","date_gmt":"2018-03-10T00:04:44","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/diseno-e-implementacion-en-fpga-de-multiplicadores-serie-paralelo-utilizando-la-aritmetica-de-da%c2%adgitos-en-serie-y-su-aplicacion-al-filtrado-en-tiempo-real\/"},"modified":"2018-03-10T00:04:44","modified_gmt":"2018-03-10T00:04:44","slug":"diseno-e-implementacion-en-fpga-de-multiplicadores-serie-paralelo-utilizando-la-aritmetica-de-da%c2%adgitos-en-serie-y-su-aplicacion-al-filtrado-en-tiempo-real","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/ciencias-tecnologicas\/diseno-e-implementacion-en-fpga-de-multiplicadores-serie-paralelo-utilizando-la-aritmetica-de-da%c2%adgitos-en-serie-y-su-aplicacion-al-filtrado-en-tiempo-real\/","title":{"rendered":"Dise\u00f1o e implementaci\u00f3n en fpga de multiplicadores serie\/paralelo utilizando la aritm\u00e9tica de d\u00edgitos en serie y su aplicaci\u00f3n al filtrado en tiempo real."},"content":{"rendered":"<h2>Tesis doctoral de <strong> Javier Valls Coquillat <\/strong><\/h2>\n<p>Esta tesis intenta realizar una contribuci\u00f3n al dise\u00f1o y construcci\u00f3n de cdsps (custom digital signal processors) en fpgas (field programmable gate arrays). Entre las diversas alternativas, se ha elegido la aritm\u00e9tica o computaci\u00f3n de d\u00edgitos en serie.  los circuitos resultantes de utilizar esta t\u00e9cnica pueden ser implementados de manera muy eficaz en un fpga. Adem\u00e1s, para una determinada aplicaci\u00f3n, permite ajsutar la frecuencia de oepraci\u00f3n en tiempo real a un valor cercano el requerido. Esto minimiza el coste en \u00e1rea, que resulta notablemente menor que la correspondiente a cualquier estructura bit paralela.  dentro de los procesadores con aritm\u00e9tica serie se estudian en detalle el operador multiplicaci\u00f3n serie\/paralelo y su aplicaci\u00f3n al filtrado fir. las principales contribuciones en esta parte son el an\u00e1lisis normalizado y la clasificaci\u00f3n de los diferentes tipos de arquitecturas atendiendo al algoritmo que implementan en hardware, la propuesta de nuevas tepolog\u00edas y finalmente, modificaci\u00f3n de los circuitos para mejorar su acoplamiento con la tecnolog\u00eda marco elegida.  la tesis se apoya por un exhaustivo trabajo experimental, en el cual se han validado m\u00e1s de 600 circuitos diferentes utilizando tecnolog\u00eda de altera. Esto ha permitido identificar las arquitecturas que mejor se adptan a una fpga con luts tipo k=4, y caracterizar cada topolog\u00eda en ancho de banda, \u00e1rea y profundidad de l\u00f3gica.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Dise\u00f1o e implementaci\u00f3n en fpga de multiplicadores serie\/paralelo utilizando la aritm\u00e9tica de d\u00edgitos en serie y su aplicaci\u00f3n al filtrado en tiempo real.<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Dise\u00f1o e implementaci\u00f3n en fpga de multiplicadores serie\/paralelo utilizando la aritm\u00e9tica de d\u00edgitos en serie y su aplicaci\u00f3n al filtrado en tiempo real. <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Javier Valls Coquillat <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Polit\u00e9cnica de Valencia<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 15\/10\/1999<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Eduardo Boemo Scalvinoni<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Antonio Garc\u00eda guerra <\/li>\n<li>enrique Mandado p\u00e9rez (vocal)<\/li>\n<li>Juan Meneses chaus (vocal)<\/li>\n<li>eduardo S\u00e1nchez (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Javier Valls Coquillat Esta tesis intenta realizar una contribuci\u00f3n al dise\u00f1o y construcci\u00f3n de cdsps (custom digital [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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