{"id":8718,"date":"1995-01-01T00:00:00","date_gmt":"1995-01-01T00:00:00","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/1995\/01\/01\/test-per-corrent-quiescent-de-fallades-tipus-pont-en-circuits-digitals-cmos\/"},"modified":"1995-01-01T00:00:00","modified_gmt":"1995-01-01T00:00:00","slug":"test-per-corrent-quiescent-de-fallades-tipus-pont-en-circuits-digitals-cmos","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/ciencias-tecnologicas\/test-per-corrent-quiescent-de-fallades-tipus-pont-en-circuits-digitals-cmos\/","title":{"rendered":"Test per corrent quiescent de fallades tipus pont en circuits digitals cmos."},"content":{"rendered":"<h2>Tesis doctoral de <strong> Eugenio Miguel Isern Riutort <\/strong><\/h2>\n<p>En la tesis se estudia la testabilidad de los fallos puente mediante test iddq y la generacion de conjuntos de test de alta calidad para detectar este tipo de fallo.El test iddq, basado en la monitorizacion de la corriente de consumo, es una metodolog\u00eda mas adecuada para la deteccion de puentes que el test logico tradicional. En el trabajo se analiza la testabilidad de los puentes cuando se utiliza el test iddq. Se proponen estrategias para la identificacion de los puentes indetectables en circuitos combinacionales y secuenciales, basadas en la utilizacion de grafos obdds y la aplicacion de la teoria clasica de maquinas de estados finitos. Se propone una estrategia de generacion de vectors de test iddq deterministas para detectar fallos puente, internos y externos, en circuitos digitales cmos, llamada cutegens.  mediante esta estrategia se generan primero vectores para el test de los puentes internos, mientras que los extremos no detectados oo estos vectores se consideran en una segunda fase. Posteriormente se realiza un proceso de compactacion de los vectores de test. El problema de la generacion de vectores para detectar puentes se traduce a un problema de generacion de test para fallos stuck-at mediante la utilizacion de logica auxiliar.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Test per corrent quiescent de fallades tipus pont en circuits digitals cmos.<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Test per corrent quiescent de fallades tipus pont en circuits digitals cmos. <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Eugenio Miguel Isern Riutort <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Polit\u00e9cnica de catalunya<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 01\/01\/1995<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Joan Figueras P\u00c1\u00a0mies<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal:  Lopez Barrio Carlos Alberto <\/li>\n<li>Yerbant Zorian (vocal)<\/li>\n<li>Michel Renovell (vocal)<\/li>\n<li>Eugenio Garcia Moreno (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Eugenio Miguel Isern Riutort En la tesis se estudia la testabilidad de los fallos puente mediante test [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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