{"id":92291,"date":"2018-03-11T10:11:15","date_gmt":"2018-03-11T10:11:15","guid":{"rendered":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/memorias-cache-adaptativas-en-procesadores-smt-adaptative-cache-memories-for-smt-processors\/"},"modified":"2018-03-11T10:11:15","modified_gmt":"2018-03-11T10:11:15","slug":"memorias-cache-adaptativas-en-procesadores-smt-adaptative-cache-memories-for-smt-processors","status":"publish","type":"post","link":"https:\/\/www.deberes.net\/tesis\/sin-categoria\/memorias-cache-adaptativas-en-procesadores-smt-adaptative-cache-memories-for-smt-processors\/","title":{"rendered":"Memorias cache adaptativas en procesadores smt (adaptative cache memories for smt processors)"},"content":{"rendered":"<h2>Tesis doctoral de <strong> Sonia L\u00f3pez Alarc\u00f3n <\/strong><\/h2>\n<p>Null el prop\u00f3sito de esta tesis es la mejora del rendimiento y la equidad de procesadores simultaneous multithreading, smt, mediante un uso m\u00e1s eficiente de la jerarqu\u00eda de memoria. La jerarqu\u00eda de memoria propuesta adapta din\u00e1micamente el tama\u00f1o ye l tie mpo de acceso a los requisitos cambiantes de la carga de trabajo, mediante la evaluaci\u00f3n de las necesidades con respecto a las memorias cache en tiempo de ejecuci\u00f3n. La decisi\u00f3n de reconfiguraci\u00f3n se lleva a cabo mediante un algoritmo de control que alcanza el mejor rendimiento posible, independientemente del n\u00famero de hebras en ejecuci\u00f3n. En nuestro trabajo demostramos que minimizar el tiempo de acceso a la memoria cache no es siempre la mejor t\u00e9cnica para mejorar rendimiento. Al contrario, cua ndo el n\u00famero de hebras en ejecuci\u00f3n es alto, el mejor rendimiento se alcaza maximizando la tasa de acceso a la memoria cache.<\/p>\n<p>&nbsp;<\/p>\n<h3>Datos acad\u00e9micos de la tesis doctoral \u00ab<strong>Memorias cache adaptativas en procesadores smt (adaptative cache memories for smt processors)<\/strong>\u00ab<\/h3>\n<ul>\n<li><strong>T\u00edtulo de la tesis:<\/strong>\u00a0 Memorias cache adaptativas en procesadores smt (adaptative cache memories for smt processors) <\/li>\n<li><strong>Autor:<\/strong>\u00a0 Sonia L\u00f3pez Alarc\u00f3n <\/li>\n<li><strong>Universidad:<\/strong>\u00a0 Complutense de Madrid<\/li>\n<li><strong>Fecha de lectura de la tesis:<\/strong>\u00a0 17\/03\/2009<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h3>Direcci\u00f3n y tribunal<\/h3>\n<ul>\n<li><strong>Director de la tesis<\/strong>\n<ul>\n<li>Antonio  Oscar Garnica Alcazar<\/li>\n<\/ul>\n<\/li>\n<li><strong>Tribunal<\/strong>\n<ul>\n<li>Presidente del tribunal: Jos\u00e9 ignacio (secretario) Hidalgo perez <\/li>\n<li>  (vocal)<\/li>\n<li>  (vocal)<\/li>\n<li>  (vocal)<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tesis doctoral de Sonia L\u00f3pez Alarc\u00f3n Null el prop\u00f3sito de esta tesis es la mejora del rendimiento y la equidad [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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