Tesis doctoral de Yaseer Arafat Durrani
Power consumption has become a primal constraint in digital electronic design. In order to optimize power at early design phases, low power techniques are now widely investigated by architecture and compiler designs. However, there are still few architecture level power estimation tools that can be used over technology generations and is capable of modeling arbitrary circuits. A key challenge in the design of low power systems is the fast and accurate estimation of power dissipation. power is a strongly pattern dependent function. Input statistics greatly influence on average power. In this thesis we propose solutions to the pattern dependence problem for intellectual property (ip) designs. This work addresses the problem of estimating power consumption at higher level of design abstraction namely, register transfer level (rtl). This power model for ips is proposed that will be used in their integration in system on chip (socs), network on chip (nocs) etc. traditional simulation-based approaches simulate the circuit using test/functional input pattern sets. Other recent approaches have used probabilistic techniques in order to cover a large set of input patterns. However, they trade-off accuracy for speed in ways that are not always acceptable. We investigate an alternative technique that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly-generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. In this thesis, a new power macro-modelling technique for rtl model of digital electronic circuits is presented. This technique allows to estimate the power dissipation of intellectual property components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (ga) using input metrics and the macro-model function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a monte carlo zero-delay simulation is performed for rtl and the power dissipation is predicted by a macro-model function. The most important contribution of the method is that it allows fast power estimation of ip-based design by a simple addition of individual power consumptions. This makes the power modelling of socs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our model, we have constructed ip-based digital systems using different ip macro-blocks. In experiments with individual ip macro-blocks, the results are effective and highly correlated, with an average error of just 1-3%.
Datos académicos de la tesis doctoral «Power macromodelling for ip-based digital systems at register transfer level (macromodelado del consumo de sistemas digitales basados en ips descritos a nivel de transferencia de registro)«
- Título de la tesis: Power macromodelling for ip-based digital systems at register transfer level (macromodelado del consumo de sistemas digitales basados en ips descritos a nivel de transferencia de registro)
- Autor: Yaseer Arafat Durrani
- Universidad: Politécnica de Madrid
- Fecha de lectura de la tesis: 13/06/2008
Dirección y tribunal
- Director de la tesis
- Teresa Riesgo Alcaide
- Tribunal
- Presidente del tribunal: José Antonio Cobos márquez
- ángel De castro martín (vocal)
- roberto Sarmiento lópez (vocal)
- marcelino Bicho dos santos (vocal)